The present invention relates to a semiconductor memory device and data elase method for it, in particular, to a Flash type Electrically Erasable and Programable Read Only Memory (Flash EEPROM) and a date erase method for Flash EEPROM.
Among the EEPROM devices, a certain type of device called Flash EEPROM which is capable of erasing data in a number of memory cells at the same time so as to achieve high speed operation has been developed. An example of the Flash EEPROM devices is described in N. Kodama, K. Saitoh, H. Shirai, T. Okazawa and Y. Hokari, "A 5 V only 16M bit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies", VLSI SYMP. 1991, pp. 75-76. According to that, a memory cell comprises a N-channel MOS transistor with a stacked type gate including a control gate and a floating gate, a write operation is achieved by using the channel hot electlon (CHE) injection to the floating gate whereas an elase operation is achieved by using the Fowler-Nordheim(FN) tunneling effect in which electrons are transported from the floating gate to a source region or a substrate. In S. Aritome, R. Shirota, R. Kirisawa, T. Endoh, R. Nakayama, K Sakui and F. Masuoka, "A RELIABLE BIPOLARITY WRITE/ERASE TECHNOLOGY IN FLASH EEPROMs", IEDM 90, pp. 111-114, there is proposed an another Flash EEPROM device in which the FN tunneling is applied to a write operation as well as an erase operation.
However, these Flash EEPROM devices have had in comonn a basic problem that some memory cell transistors are over-erased during the erase operation. In order to prevent it, a pre-write/erase-verify method has been adopted as described in, for example, NIKKEI MICRODEVICE, March, 1990, pp. 72-76, or Japanese patent application, publication number: 01-273296. This problem and the pre-write/erase-verify method will be described with reference to FIGS. 9-12.
FIG. 9 shows a typical structure of memory cell transistors used in a Flash EEPROM. FIG. 10 shows threshold voltages of the memory cell transistors. While a non-written memory cell transistor has a threshold voltage of about 2 V, since electrons are transported to a floating gate by a CHE injection or an FN tunneling during a write operation, a written memory cell transistor has a threshold voltage of about 7 V. In this case, the power supply voltage of the device is 5 V as shown in FIG. 10. So that when a memory cell is selected and a control gate of a memory cell transistor becomes at 5 V, the memory cell transistor becomes conductive or non-conductive in accordance with whether it is written or not, and when the memory cell is not selected and the control gate is at 0 V, the transistor is in non-conductive state. During a erase operation, the electrons in a floating gate are transported to a source region or a substrate by FN tunneling so that a threshold voltage of a written memory cell transistor is decreased to around 2 V, preferably the same voltage as that of non-witten transistors. Therefore, because of the FN tunnelings applied to the erase operation which requires very small currents, the erase operation can be performed for a number of memory cells at the same time so that it is possible to increase the operation speed of the device.
However, in the erase operation, some of memory cell transistors are over-erasedand and become in depression states having negative threshold voltages. In this condition, the over-erased memory cell is continuously in a conductive state regardless of whether or not it is selected and the device fails to function properly.
In order to prevent such a problem, according to the pre-write/erase-verify method, memory cells are written in advence to a erase opertion. This pre-write poeration is performed by using the FN tunneling effect with reducing the current consumption so that it can be applied to all memory cells, or particular memory cells which correspond to certain blocks of the device or so, at the same time. Owing to this operaion, the threshold voltages of the non-written memory cell transistors are raised as shown in FIG. 11. However, since the gate insulating films through which the FN tunneling effect is performed are very thin oxide films which tend to vary through manufacturing processes in their certain properties such as thicknesses and involve oxide ridges, it is difficult to achieve the FN tunnelings uniform in amount of electron transportation for a number of memory cell transistors and the threshold voltages of the memory cell transistors after FN tunnelings vary from each other and are scattered in a broad range as shown in FIG. 11. Therefore, subsequently to the pre-write, in this prior art device, the erase operation is performed on a step-by-step basis with the erase-verify operations which are performed alternately with each step of the erase operation as shown in FIG. 12. During the erase-verify pperation, read out operations for all memory cells are peformed. If any memory cells are not erased, the erase operation is performed again. So that it is possible to adjust the threshold voltages within the range between the control gate voltages in a selected and a non-selected states, that is, 0 V and 5 V as shown in FIG. 11.
Accordingly, since the pre-write operation is performed by using the FN tunneling effect which requires considerably long time and a high voltage in order to raise the threshold voltage of the non-written transistors so high, near to that of written transistors, the operation speed of the device is decreased and the circuits becomes large. Moreover, since the erase-verify operations are needed, the operation speed of the device is highly decreased and current consumption becomes large. Furthermore, since the prior art device is applied with the FN tunneling effect twice, that is, FN tunneling pre-write and FN tunneling erase, the variance of the threshold voltages after the erase operation becomes considerably large so that it may be occur that some memory cell transistors are not erased and/or some others are over erased after the erase operation.